A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist.
A layout file is created from the placement and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process.
One or more photomasks are created from the layout file for the photolithography of each layer. Photomasks are used to transfer the layout pattern onto the physical layer on the wafer. A photomask, or mask, provides an image of the desired physical geometries of the respective integrated circuit layer. Passing light through the mask projects the layout pattern for the layer onto the wafer. An imaging lens system projects and focuses the layout onto the substrate. The projected light pattern interacts with a photosensitive resist coating on the wafer and, resist portions that are exposed to light are rendered either soluble or insoluble in a developer solution, depending on the type of the photoresist. Accordingly, the mask pattern is transferred into the photo-resist by optical projection and chemical reactions. The photo-resist pattern is subsequently transferred to an underlying layer by an etch process. Most commonly, plasma containing chemically-selective reactive ions is used to etch high-aspect ratio trenches and holes with close to vertical sidewalls.
With a continuing desire to provide greater functionality in smaller packages and the evolution of processing technologies, IC feature geometries are being driven to smaller and smaller dimensions. However, the ability to project an accurate image of increasingly smaller features onto the wafer is increasingly limited by the inherent limitations of conventional semiconductor manufacturing processes. To address these inherent difficulties when manufacturing at extremely small feature sizes, many fabrication facilities now require stringent compliance with many design rules.
For example, with modern manufacturing and processes, design rules may be implemented which allow only certain widths during the creation of shapes on certain layers, e.g., during the creation of FinFET regions in an IC design. These rules restrict the width of an object (e.g., rectangle or polygon) to certain specified width dimensions on the layout. Any deviation from these allowable widths would constitute a design rule violation.
Various approaches can be taken by a designer to comply with such rules. One possible approach is to provide “snapping” in a layout editing/creation tool, where objects inserted into a layout are automatically moved to a legal dimension for the object. The problem with this approach is that in some cases, a designer may wish to have the flexibility to insert an object that does not currently meet the allowable width rule. However if snapping is turned on, the snapping approach will not allow this to occur.
To illustrate, consider FIG. 1, where portion 102a illustrates how a designer using a custom editing tool may use a user interface to fix a first edge of a rectangle (e.g., by clicking a location in the layout to fix the left side of the rectangle), and then move the cursor to direct the location of a second edge of the rectangle (e.g., in the right-hand direction as shown in the figure). The dashed line indicates the closest legal edge location for the rectangle. Assume that the designer does not wish to place the right-hand edge of the rectangle at that legal location. Instead, as shown in portion 102b, the designer intends for the right-hand edge of the rectangle to be located just short of that location. This may occur, for example, if the designer intends a subsequent action to insert another object that abuts the right-hand side of the rectangle, which would cause the overall combined width to comply with a legal allowable width. However, instead of allowing the designer to make the right-hand edge at the desired location (which is currently invalid), as shown in portion 102c, the system will cause the right-hand edge to automatically snap to the legal edge location. This lack of control given to the designer may create enough frustration such that the designer will eventually turn off the snapping functionality, requiring the designer the thereafter manually ensure and measure edge locations if the intent is to place the edge on a valid location. This manual approach creates many inefficiencies, since even in the cases where the designer intends to place an edge right on a legal location, this will have to be done manually.
As is evident, the dedicated manual approach is inefficient, and is likely to be error-prone, since the designer is more likely to unintentionally place objects with illegal dimensions at illegal locations. However, the automated snapping approach is too constrictive and lacks enough control for the designer.
Therefore, there is a need for an improved approach to facilitate the design of electronic circuits, particularly with respect to placement and editing of objects with regards to allowable dimensions and edge locations.